Embodiments relate to a semiconductor device and a method of manufacturing a semiconductor device.
Semiconductor devices may be used in various technologies, including switching mode power supplies, lamp stabilization and/or motor driving circuits. A depletion type MOSFET (DMOSFET) using a planar diffusion technology, for example a laterally diffused metal oxide semiconductor (LDMOS) transistor, may be developed. A lateral double diffused metal oxide semiconductor (LDMOS) may be a majority carrier device and/or a lateral power device which may have relatively rapid switching response and/or relatively high input impedance. Example FIG. 1 is a sectional view illustrating an LDMOS device.
Referring to FIG. 1, an LDMOS device may include P-type epitaxial layer 10 on and/or over a semiconductor device, deep n well (DNWELL) 20, gate dielectric 41, gate 40, spacer 42, P-body 50, isolation layer 30 which may define a semiconductor region and/or drain expansion isolation layer 32. An LDMOS device may include ion-implanted region 52 of a first conductivity type on and/or over P-body 50 at one side of gate 40, first ion-implanted region 54 of a second conductivity type between ion-implanted region 52 of a first conductivity type and gate 40 and/or a second ion-implanted region 60 of a second conductivity type at a side of drain expansion isolation layer 32. Drain expansion isolation layer 32 may be a layer formed by expanding a portion of gate dielectric 41. A current may flow from first ion-implanted region 54 of a second conductivity type, for example a source region, through a surface of drain expansion isolation layer 32 to second ion-implanted region 60 of a second conductivity type, for example a drain region.
An LDMOS device may be used as a switching device, and/or a channel length 1 of an LDMOS device may be relatively shortly formed to drive a relatively large amount of a current. An LDMOS device may be designed such that a doping concentration of P-body 50 is high enough to protect from a relatively high voltage, to prevent a punch-through breakdown phenomenon when a reverse bias may be applied. However, current may flow through an inversion layer formed on and/or over a surface of P-body 50, under the gate 40, when a voltage may be applied. Electron mobility of an inversion layer may be relatively lower than a bulk region of a semiconductor substrate, on-resistance which may be a main parameter of an LDMOS device may be maximized, and/or current drivability may be minimized.
Accordingly, there is a need for a semiconductor device and a method of manufacturing a semiconductor device which may have an accumulation channel structure, in contrast to a channel structure in which a current flows through an inversion layer formed on and/or over a surface of a P-body when a voltage may be applied.